As memory devices continue to be scaled to smaller processing geometries and increased densities, the error rate tends to increase. There are multiple mechanisms applied to perform error checking and correction (ECC) to data stored in memory devices, and improve the reliability, accessibility, and serviceability (RAS) of higher density memory devices. One technique involves the striping of data across multiple memory devices, similar to data striping in RAID (redundant array of independent drives) implementations of storage devices. The techniques enable the recovery of data even in the event that an entire memory device fails. The recovery of data in the event that an entire memory device fails can be implemented by Chipkill by IBM (International Business Machines), Extended ECC by Sun Microsystems, DDDC (double device data correction) by Intel Corporation, and others. All trademarks are the property of their respective owners. Features that enable recovery from a full memory device failure are commonly implemented in server devices, where the increased cost of such implementations is seen to justify the improved RAS that such features provide.
It will be understood that implementation of such features typically requires additional hardware. Specifically, more robust ECC implementations include more memory devices to achieve the redundancy of information used to provide the ECC. For a given data access, the system can distribute the data across a large number of devices, and then implement an ECC code that can correct for a complete failure of any one of the devices. It is common to use 18 or 36 separate DRAM (dynamic random access memory) devices to achieve robust ECC implementations. However, the large number of devices traditionally needed for recovery from complete device failure may not be practical for some contexts.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.